Printing telegraph apparatus



United States Patent O 3,492,422 PRINTING TELEGRAPH APPARATUS FrederickPercival Mason, Sutton, and Alfred Lawrence Joseph Luke Suban, London,England, assignors to Creed & Company Limited, Hollingbury, Brighton,Sussex, England, a British company Filed May 3, 1967, Ser. No. 635,895Claims priority, application Great Britain, May 3, 1966, 19,418/66 Int.Cl. H041 /34 U.S. Cl. 178-26 2 Claims ABSTRACT 0F THE DISCLOSURE Thisinvention relates generally to apparatus for converting start-stop,serial-mode signals into parallel-mode signals, and in particular tomeans for improving the timing of the instants at which theparallel-mode output signals are offered to a utilization device, suchas a printer or perforator, operating in either start-stop or neverstopmanner.

In a conventional serial-to-parallel converter, the code elements of areceived combination are loaded serially into a first store under thecontrol of a start-stop timebase. When the code becomes valid in thefirst store, it can be offered to the utilization device by opening aset of gates, the code elements generally being concurrently transferredinto a second store.

However the instants at which successive transfers can occur areIfixedly related to the arrival instants of successive start signals.

Moreover the presence of line distortion can cause the incidence timeinterval, between two consecutive start signals, to become less than theinterval at which they were transmitted. Therefore it follows that thelifetime of a code combination in the second store can be less than thenominal transmission interval. The cycle time of any utilization devicecannot be greater than the least lifetime of the code in the secondstore and is consequently less than the nominal transmission interval.

It is this situation that can be improved by adopting the inventiondescribed herein.

Accordin-g to the invention in its broadest aspect there is providedserial-to-parallel code conversion apparatus comprising a storage devicethat is arranged to be serially loaded under the control of aconventional start-stop timebase, which apparatus is characterised bythe incorporation of auxiliary timing means whose output pulse controlsthe opening of a set of gates through which the parallel-mode signalsfrom the connection apparatus are offered to a utilization device, theauxiliary timing means being prepared by a signal from the start-stoptimebase and triggered to yield a further output pulse when it hasmeasured out a prescribed time interval whose duration is greater thanthe least interval between the arrival of consecutive start signals butless than the nominal transmission interval between successive startsignals.

If the invention is employed with a start-stop utilization device, theact of offering the parallel-mode signals 3,492,422 Patented Jan. 27,1970 to the device can be made effective to start a cycle of operationthereof.

Before describing how the invention may be used with a so-calledneverstop utilization device, it is deemed advisable to identify clearlythe principal characteristics of a neverstop system.

By a neverstop device is meant one having contiguous operating cyclesthat are effected continuously. lIt is this characteristic that permitsthe mechanical version of a neverstop device, such as a neverstopprinter, to avoid the need for a clutch that often demands frequencymaintenance attention.

In a neverstop system it is arranged that pulses are vemitted toannounce the instants of passage from one operating cycle to another.

It will be appreciated that there can be an entirely random phaserelationship between the pulses emitted by the neverstop system and theinstants at which parallel-mode codes are offered at the output of theserial-to-parallel converter.

Nevertheless, the emitted pulses can still be used t0 interrogate thestore into which the signals are offered under the control of auxiliarytiming means, by using pulses of short duration to open a second set ofgates.

In exactly the same manner as for a start-stop utilization device, theinvention allows the neverstop system to have a cycle time almost asgreat as the transmission cycle time.

However, in common with most utilization devices, a neverstop printerneeds a parallel-mode input that is sustained for the whole printingcycle. This requirement is fulfilled by providing a further stage ofstorage into which the signals are transferred when the said second setof gates are opened by the interrogation pulses.

Since at the time of occurrence of the interrogation pulse, there may beno code waiting-at the converter output, a signal must be provided thatindicates to the utilization device, by its presence or absence, whetheror not a code is awaiting processing.

The exact means whereby the system according to the invention cooperateswith a neverstop printer or perforator will be better understood fromthe following detailed description of such an embodiment.

This embodiment is illustrated in FIGURES l and la of the accompanyingdrawings which, when placed together, are in the form of a blockschematic diagram showing a neverstop printer responsive to receivestartstop signal combinations.

In this embodiment it is assumed that the received signal combinationscomprise an immutable start element, five permutable code elements andan immutable stop element of indefinite duration. These signalcombinations are received in serial mode over the input line on the leftof the figure.

The detection of a stop-start transient by the detector SD triggers afirst time base TB1 whose distributed output samples the incoming codecombination at the midpoints of successive elements. A first(sequential) store S1 is reset as necessary by the sampled start signal,and is then loaded with the incoming code combination as gates G1 areopened singly and successively by the distributed output pulses of thestart-stop timebase TB1.

The received code combination becomes valid in store S1 when the fifthpermutable element is sampled; whereupon a first memory (bistable) M1changes to its set condition (1). The output of M1 triggers a l-shotauxiliary timebase TBZ, Whose output immediately prevents any furthertriggering of itself by energizing a inhibit gate I, and also resets asnecessary a second (concurrent) store S2. After a short delay to allowstore S2 to be properly reset, a second set of gates G2 are opened by adifferential pulse from the timebase TBZ, to transfer the valid codefrom S1 to S2, reset memory M1 and set a further memory M2.

With memory M2 set, a pulse from a further (neverstop) timebase TB3resets as necessary a (concurrent) store S3 and a memory M3, then aftera short delay opens gates G3 to transfer the valid code from S2 to S3,and changes memory M3 to its set condition. Since the minimum lifetimeof the valid code in S2 is determined by the l-shot auxiliary timebaseTBZ, the interval between the pulses from the neverstop timebase TB3 issuch that at least one pulse occurs during this lifetime. It is to beunderstood that the neverstop timebase TB3 could be a purely mechanicaldevice directly operated by the printing mechanism.

The output of memory M3 resets memory M2 and causes the marshalling ortranslating system MT to select the type or function in accordance withthe parallel code in S3 and, after a delay to allow marshalling to takeplace, energizes the type or function actuator A. It is to be understoodthat the marshalling system MT could also control the operation of atape punch in addition to, or instead of, a printer.

When the next start signal element arrives, the operation of the systemwill depend on the interval that has elapsed since the previous startsignal element was received. If the interval is equal to or greater thana normal character period, the auxiliary timebase TBZ will havecompleted its cycle before the new code becomes valid to change memoryM1 to its set condition. Therefore the sequence of operation will be asdescribed for a previous i code. However, if the interval is less than anormal character period the auxiliary timebase TBZ will not havecompleted its cycle when memory M1 becomes set to denote that the newcode is valid in store S1. Nevertheless, as soon as the auxiliarytimebase does complete its cycle, it is re-triggered by memory M1.Although the period of the auxiliary timebase is made almost equal to acharacter period, the lifetime of the valid code in S1 is alwayssuficient to allow the auxiliary timebase to complete its previous cycleand be re-triggered to open the gates G2 before S1 can be reset by thearrival of a further start signal element.

When no further start signal elements are received, memories M1, M2 andM3 are all reset as the previous code is processed. Although thenevertstop timebase TB3 continues to emit regular pulses, themarshalling system MT receives no further command signals from memoryM3.

What we claim is:

1. An improved serial-to-parallel code converter of the type having aiirst store arranged to be serially loaded with received code signals byway of a iirst set of gates under the control of an original start-stoptimebase and a second store coupled to said iirst store and arranged tobe concurrently loaded with said signals by way of a second set ofgates, wherein the improvement comprises an auxiliary timebase circuit,coupled between said original timebase and said second set of gates, forproviding an independent timebase which permits full use of convertedcode signal combinations by a utilization device in cases of receivedsignal distortion, said auxiliaiy timebase circuit including:

a bistable memory element coupled to the original time-l base, saidmemory element being set by said original timebase whenever a codecombination is validly entered in said first store;

an inhibiting device, having afirst input coupled to said memory elementand an inhibiting second input, said inhibiting device providing anoutput in response to a corresponding input from said memory element inthe absence of a signal at said inhibiting input; and

a monostable device, having a predetermined time period of operationwhich is greater than the least interval consecutive input code startsignals but less than the normal interval between said start signals,said monostable being input coupled to said inhibiting device and beingoutput coupled to the inhibiting second input of said inhibiting gate,to said second set of gates, and to said memory element, said monostabledevice providing an output of said predetermined duration in response toa validly entered code combination in said rst store, which outputinhibits the inhibiting device for said duration, resets said memoryelement, and opens said second set of gates to allow the transfer of thecode combination in the first store to said second store, whereby asubsequent setting of said memory element from a prematurely arrivedsucceeding code combination will be retained for a time sucient to allowsaid utilization device to make full use of the preceding codecombination in said second store, while the transfer of said succeedingcode combination to the second store is permitted before it can beerased by a further succeeding code combination to be entered in saidfirst store.

2. Apparatus according to claim 1 further including a concurrent thirdstore coupled to said utilization device, a third set of gates coupledbetween said second and third stores for controlling the transfer ofcode signals therebetween, a control gate coupled to said third set ofgates for initiating said transfer of code signals, a seccond bistablememory element coupled to the output of said monstable device and tosaid control gate for priming said control gate in response to an outputsignal from said monostable device, a further time base circuit coupledto said control gate for providing enabling signals to said controlgate, and a third bistable memory element coupled to said control gateand said utilization device for generating a triggering signal to saidutilization device in response to a signal from the enabled controlgate.

References Cited UNITED STATES PATENTS 2,961,649 l1/l960 Eldredge et al.340--1463 1,576,167 3/1926 Wheeler, et al 178--l7.5 3,267,460 8/ 1966Merrell, et al. 340--347 3,376,384 4/ 1968 Achramowicz 178--26 THOMAS A.ROBINSON, Primary Examiner M. M. CURTIS, Assistant Examiner U.S. Cl.X.R.

